1. Field of the Invention
The present invention relates generally to a dynamic flip flop that, at points of variation in clocks, prevents a signal line to be brought into a floating state from maintaining a voltage below a substrate voltage level when using a P-type semiconductor substrate and prevents a signal line to be brought into a floating state from maintaining a voltage exceeding a substrate voltage level when using an N-type semiconductor substrate.
2. Related Background Art
FIG. 7 shows an example of a circuit diagram illustrating a dynamic flip flop conventionally used. As shown in FIG. 7, a dynamic flip flop has been known that is composed of a transmission gate 101, an inverter 102, a transmission gate 103, and an inverter 104. The transmission gate 101, into which a signal D is input, outputs a signal M in synchronization with a clock C1 and a clock C1X. The inverter 102 inverts the signal M to output a signal MX. The transmission gate 103, into which the signal MX is input, outputs a signal QX in synchronization with a clock C2 and a clock C2X. The inverter 104 inverts the signal QX to output a signal Q. FIG. 8 shows a diagram illustrating an operation of the dynamic flip flop conventionally used.
In such a dynamic flip flop, however, when the conduction in the transmission gate 101 ceases according to timing of the clock C1, the signal M is brought into a floating state. When the transmission gate 101 is in a conducting state and the signal M is at a substrate voltage level, the signal M maintains a voltage below the substrate voltage level due to coupling caused by parasitic capacitance generated between the clock C1 and the signal M at the instant when the conduction in the transmission gate 101 ceases. Similarly, when the conduction in the transmission gate 103 ceases according to timing of the clock C2X, the signal M is brought into a floating state. When the transmission gate 103 is in a conducting state and the signal M is at a substrate voltage level, the signal QX maintains a voltage below the substrate voltage level due to coupling caused by parasitic capacitance generated between the clock C2X and the signal QX at the instant when the conduction in the transmission gate 103 ceases. When using a P-type substrate, a PN junction diode between the substrate and a drain with a voltage below the substrate voltage level is subjected to a forward bias and a substrate current flows. When the substrate current flows, electrons are generated. The electrons thus generated are minority carriers in the P-type substrate and become stray carriers. The stray carriers diffuse inside the semiconductor substrate. For example, in a semiconductor device having a built-in light-receiving element such as a photoelectric conversion device, there has been a problem of causing fixed pattern noise since electrons as stray carriers contaminate the light-receiving element and the degree of contamination is not uniform over the whole light-receiving element.
A dynamic flip flop of the present invention is characterized by being provided with switches for short-circuiting signal lines to be brought into a floating state to the substrate side according to timing of clocks.